AutoESL Technical Seminar

AutoESL Technical Seminar

Data: mercoledì 2 maggio 2012
Orario: dalle 10:00 alle 16:00
Luogo: Mappa
Costo: Gratuito



Programma

09:00 – 09:15 | Welcome and Introduction: Xilinx 7 Series update

09:15 – 10:15 | Design flows: HLS with AutoESL and Model Based Design with System Generator

10:15 – 11:15 | AutoESL Example 1: Optimizing an image processing routine – Using the AutoESL compiler directives

11:15 – 11:30 | PAUSA

11:30 – 12:00 | Importing AutoESL generated VHDL in System Generator as a black box – Interoperability between AutoESL and System Generator

12:00 – 13:00 | AutoESL Example 2: Linear algebra matrix multiplication – Code profiling & partitioning; implementing the matrix multiplier in HW on Zynqâ„¢-7000

13:00 – 14:30 | PAUSA PRANZO

14:30 – 15:30 | Image processing demonstration on a Zynq development board – AXI connected peripherals designed with AutoESL

15:30 – 16:00 | Conclusion



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